1. Technical Field
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a delay-locked loop and a test method thereof.
2. Description
A synchronous memory device synchronizes with an external clock signal to input and output data. A high-speed memory device generally uses a delay-locked loop (DLL) to synchronize data with an external clock signal.
FIG. 1 is a block diagram of a general semiconductor memory device having a DLL. Referring to FIG. 1, the semiconductor memory device includes a DLL 110 and a normal pass 160.
The DLL 110 includes a variable delayer 120, a replica pass 130, and a phase detector 140. The variable delayer 120 delays a clock signal CLK/CLKB for a predetermined period of time in response to a delay control signal CON output from the phase detector 140 to generate an internal clock signal IN_CLK. The normal pass 160 outputs internal data IDATA outside the semiconductor memory device in response to the internal clock signal IN_CLK. The DLL 110 includes the replica pass 130, which is a replica of the normal pass 160, in order to compensate for a time delay occurring in the normal pass 160. The phase detector 140 compares a phase of the clock signal CLK/CLKB with a phase of a replica clock signal DQR to control a time delay in the variable delayer 120 so that the replica clock signal DQR is in phase with the clock signal CLK/CLKB.
Accordingly, when the phase of the replica clock signal DQR synchronizes with the phase of the clock signal CLK/CLKB, data DQ output from the normal pass 160 having the same time delay as the replica pass 130 also synchronizes with the clock signal CLK/CLKB.
Therefore, in order to accurately lock the DLL 110, complicated circuits of the normal pass 160 must be exactly replicated as circuits of the replica pass 130 on a one-to-one basis. With an increase in the high speed of the semiconductor memory device, the clock characteristics of the replica pass 130 of the DLL 110 are quite important. In particular, as the operational frequency of the semiconductor memory device gets faster and the operational voltage thereof gets lower, the reliability of a clock signal in the replica pass 130 degrades, which may cause the DLL 110 to abnormally operate. In other words, as the operational frequency of a semiconductor memory device gets higher and the operational voltage thereof gets lower, the possibility for a DLL to abnormally operate may be higher due to a replica pass.
As described above, a DLL is highly likely to malfunction due to a replica pass. However, it is not easy to check under a general DLL test whether the DLL operates normally or abnormally due to the replica pass. Consequently, the complicated replica pass should be optional in a predetermined test mode to easily check whether the DLL malfunctions due to the replica pass.
Accordingly, it would be desirable to provide a semiconductor device having a DLL in which a check can be easily achieved whether the DLL operates normally or abnormally. It would also be desirable to provide a test method capable of easily checking whether a DLL operates normally or abnormally in a semiconductor device having the DLL.
According to one aspect of the present invention, there is provided a semiconductor device including a variable delayer, a normal pass, a replica pass, and a phase detector. The variable delayer delays a clock signal for a predetermined period of time to generate an internal clock signal. The normal pass outputs data read from a memory cell outside the semiconductor device in response to the internal clock signal. The replica pass has a substantially identical time delay to the normal pass and delays the internal clock signal to generate an output signal. The phase detector compares a phase of the clock signal with a phase of a predetermined feedback clock signal to control a time delay in the variable delayer. Here, the internal clock signal instead of the output signal from the replica pass is output as the predetermined feedback clock signal in a predetermined test mode.
Preferably, the replica pass includes components that substantially equal components of the normal pass. That is, the replica includes components that are replicas of the normal pass on a one-to-one basis.
The semiconductor device further includes a multiplexer that selects one of the output signal from the replica pass and the internal clock signal to output the selected signal as the predetermined feedback clock signal in response to a predetermined mode signal.
According to another aspect of the present invention, there is provided a semiconductor device including a normal pass and a delay-locked loop. The normal pass receives data read from a memory cell and outputs the received data in response to an internal clock signal. The delay-locked loop receives an external clock signal to generate the internal clock signal, and includes a replica pass which compensates for a time delay in the normal pass. The delay-locked loop forms a loop excluding the replica pass in a predetermined test mode, while the delay-locked loop forms a loop including the replica pass in a non-test mode.
The delay-locked loop includes a variable delayer, a multiplexer, and a phase detector. The variable delayer delays the clock signal for a predetermined period of time to generate the internal clock signal. The multiplexer selects one of an output signal from the replica pass and the internal clock signal to output the selected signal as a feedback clock signal in response to a predetermined mode signal. The phase detector compares a phase of the clock signal with a phase of the feedback clock signal to control the time delay in the variable delayer.